Annotation

Annotation: This paper investigates microarchitectures of processor cores intended for synthesis on field-programmable gate array (FPGAs) and for use within heterogeneous massively parallel computing systems on chip. The relevance of this work is determined by the limitations of further performance scaling of general-purpose processors and the necessity of transitioning toward specialized computing architectures optimized for specific classes of algorithms. The aim of the study is to analyze promising architectures of synthesizable control processor cores and to evaluate the impact of their microarchitecture design decisions on timing and resource characteristics when employed as components of massively parallel computing systems. The paper considers the requirements imposed on processor cores operating within computing clusters and identifies the reason for the inefficiency of conventional general-purpose processors under conditions of large-scale replication on a single chip. The theoretical section examines processor architectures with minimal pipeline depth implementing “fetch-execute” and “fetch-decode-execute” schemes. The application of data forwarding mechanisms in both the datapath and the control flow path is analyzed, and their influence on critical path formation and latency caused by violations of linear instruction execution order is discussed. Experimental studies were conducted using the Vivado computer-aided design environment for FPGA devices of the Artix-7 and Virtex UltraScale+ families. A comparative evaluation of single-cycle, two-stage and three-stage pipeline architectures with and without bypass mechanisms was performed. The primary evaluation metric was the maximum achievable clock frequency determined through static timing analysis. The obtained results demonstrate that increasing the number of pipeline stages has a significantly greater impact on the achievable frequency characteristics of the processor core than the use of data forwarding schemes, whose influence is limited by the specific features of the considered class of control processors. The results demonstrate that increasing the number of pipeline stages has a significantly greater impact on the achievable frequency characteristics of the processor core than the use of data forwarding schemes, whose influence is limited by the specific features of the considered class of control processors. The results of this study can be applied in the design of specialized and heterogeneous FPGA-based computing systems, as well as in the development of processor cores for massively parallel computing architectures.