Annotation

Annotation: The article examines issues related to organizing data propagation routes on the chip of a hardware platform designed for computing clusters based on programmable logic. Modern trends requiring massively parallel systems for data processing are outlined. The role of high-speed input/output interfaces is noted, as well as the resulting practical demand for increasing data-path frequencies for information received from them. The aim of the research is to improve the efficiency of the technical implementation of the data path in systems with massively parallel architectures. The objective of the research is to develop an iterative approach that takes into account the features of the hardware platform topology alongside the RTL architecture of the designed solution. Particular emphasis is placed on the fact of predetermined placement and routing, which contributes to enhancing the technical characteristics of the final design. The article presents results obtained from experiments conducted for different types of computing cores, as well as for various strategies used at the placement and routing stages of the design flow. Among the main comparison criteria are timing slack indicators along data propagation paths, which reflect the maximum operating clock frequency of the device, as well as the ability to preserve additional placement and routing constraints. An FPGA integrated circuit was used as the hardware platform to reduce the influence of different PDK. Analysis of the results shows improvements in technical characteristics in each experiment, as well as the flexibility of applying the proposed approach while considering additional placement and routing constraints associated with the use of DFX technology.