Annotation

Annotation: This paper inaugurates a series of research aimed at investigating configuration variants of pipeline special-purpose computing systems employing dedicated hardware blocks. The objective of the research is to extend the applicability of the system-level approaches previously developed by the Laboratory of Special-Purpose Computing Systems at RTU MIREA for constructing logical and topological representations of pipeline special-purpose computing systems utilizing dedicated hardware blocks embedded in field-programmable gate arrays (FPGAs). The relevance of developing specialized computing devices for tasks requiring minimal response time and high performance is discussed. The paper reviews the fundamental concepts and principles underlying the construction of logical and topological representations of special-purpose computing systems, as well as the issues of ensuring consistency between different representation variants while preserving the intended design characteristics. System-level approaches developed by the Laboratory of Special-Purpose Computing Systems at RTU MIREA for constructing representations of pipeline computing systems are presented. The applicability of these approaches to the design of pipeline special-purpose computing systems based on FPGA dedicated hardware blocks is examined. Particular attention is paid to Digital Signal Processing (DSP) blocks, which are widely used to implement multiply-accumulate operations, digital signal processing algorithms, and neural network computations. The architectural features of the DSP48E1 block and the specifics of its placement within AMD Artix-7, Kintex-7, and Virtex-7 FPGA families are analyzed. An automated framework has been developed to generate special-purpose computing system configurations, construct their topological representations, and obtain detailed implementation reports. Experimental results demonstrate the influence of pipeline depth on the achievable operating frequency of the special-purpose computing system, as well as significant differences in critical path delay across different representation variants. The paper concludes by outlining directions for further research.